DocumentCode :
972409
Title :
Identification and measurement of scaling-dependent parasitic capacitances of small-geometry MOSFET´s
Author :
Wang, Chih Hsin
Author_Institution :
Adv. Custom Technol., Motorola Inc., Phoenix, AZ, USA
Volume :
43
Issue :
6
fYear :
1996
fDate :
6/1/1996 12:00:00 AM
Firstpage :
965
Lastpage :
972
Abstract :
The scaling dependence of the gate-to-source capacitance in strong accumulation Cgsacc is investigated for the first time to study the parasitic capacitances for MOSFETs with different gate-lengths. Results show a gate-length Lgate dependent characteristic for Cgsacc and is consistent with the results from numerical device simulation. The result is found to be different from the widely used assumption in the literature, and is believed to be reported for the first time. The gate-length dependent C gsacc characteristic is due to the top side capacitance, and is verified through careful device characterization and numerical device simulation. A measurement technique is further developed to determine Ctop for small geometry MOSFETs. The technique is demonstrated on actual transistors with no special test devices required. Based on the technique, a sub-linear dependent relationship is found for the dependence of Ctop on Lgate, and is in close agreement with the results predicted by theory. Results also indicate that Ctop is about 8-13% of the measured total Cgsacc, which corresponds to a nonnegligible portion of the total capacitance, and needs to be considered for future device design, characterization and modeling. The impact of Ctop on CMOS inverter gate delay is also investigated. Results indicate Ctop adversely impact the gate delay by as much as 5.5% as supply voltage is scaled down to 1 V
Keywords :
MOSFET; capacitance; capacitance measurement; delays; semiconductor device models; semiconductor device testing; CMOS inverter gate delay; device characterization; gate-length dependent characteristic; gate-to-source capacitance; measurement technique; numerical device simulation; scaling-dependent parasitic capacitances; small-geometry MOSFETs; strong accumulation; top side capacitance; Capacitance measurement; Delay; Geometry; Inverters; MOSFETs; Measurement techniques; Numerical simulation; Parasitic capacitance; Semiconductor device modeling; Testing;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.502131
Filename :
502131
Link To Document :
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