Parallel architectures for higher-radix division

A general approach for designing units for higher-radix division is outlined which is based on several subunits operating in parallel. A lower-radix-division unit is used as the building block of the architecture, and the division step is split into two phases which are carried out in parallel. It is shown that the proposed architecture permits the design of units for higher-radix division with digit-selection tables requiring only few supplementary input bits with respect to the tables used by lower-radix division systems.