Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements

With clock frequencies in the multigigahertz range, wide wires in the power and clock distribution networks suffer from prominent frequency-dependent effects. To overcome the simulation problem of such circuits, a guaranteed stable and parallelizable model order reduction technique is proposed that can handle frequency-dependent elements by construction. The basic idea is to match the output at multiple frequencies with a reduced order function. Once the reduced function is known, it becomes straightforward to calculate the time-domain response. Since this technique works in the frequency domain, it does not require replacement of frequency-dependent elements with equivalent constant RLC subcircuits, significantly reducing the size of equivalent circuits of wide power and clock distribution networks. With parallel computation, the proposed technique obtains time-domain responses in comparable time to calculate the first moment in AWE. Simulations have shown that as few as six frequency points are needed for coupled RC circuits and up to 50 frequency points are needed for complex RLC circuits. To test its ability of handling frequency-dependent elements, a sample circuit with frequency-dependent elements is used that is about 30% of the size of the equivalent circuit with constant RLC elements used in SPICE. In all cases, the proposed technique gives accurate and stable time-domain responses.