A 1.71-million transistor CMOS CPU chip with a testable cache architecture

Author

Saito, Yuichi ; Shimazu, Yukihiko ; Shimizu, Toru ; Shirai, Kenji ; Fujioka, Isao ; Nishiwaki, Yoshitetsu ; Hinata, Junichi ; Shimotsuma, Yoshiki ; Sakao, Masayoshi

Author_Institution

LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1071

Lastpage

1077

Abstract

A 1.71-million transistor CISC CPU chip for the business computer has been developed. The chip is implemented in a 0.8-μm CMOS double-polysilicon double-metal technology. The 16.3-mm×12.7-mm device contains a 16-kilobyte cache and 192 entries TLB and operates at 40 MHz. The sustained high performance in a complexed instruction set has been realized by a large horizontal microprogram that controls two 32-b ALU´s. The cache and TLB employ a 77-μm² SRAM using load resistors formed by the second polysilicon; these are accessed in one-half clock cycle and are tested at an 8 bytes per clock rate utilizing a new test strategy

Keywords

CMOS integrated circuits; buffer storage; computer architecture; memory architecture; microprocessor chips; microprogramming; 0.8 mum; 1.71-million transistor; 16 kB; 40 MHz; ALU; CISC CPU chip; CMOS CPU chip; CMOS double-polysilicon double-metal technology; SRAM; TLB; business computer; complexed instruction set; horizontal microprogram; load resistors; one-half clock cycle; second polysilicon; test strategy; testable cache architecture; CMOS technology; Central Processing Unit; Clocks; Computational modeling; Computer architecture; Control systems; Large scale integration; Microprocessors; Random access memory; Testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245584

Filename

245584