Title :
A 6-ns cycle 256-kb cache memory and memory management unit
Author :
Heald, Raymond A. ; Holst, John C.
Author_Institution :
Adv. Processor Div., Intergraph Corp., Huntsville, AL, USA
fDate :
11/1/1993 12:00:00 AM
Abstract :
A 6-ns cycle, 7.7-ns access cache memory and memory management unit (CAMMU) chip has been developed. The circuit includes two 5-ns 128-kb cache memories, two 4-ns 64-entry fully associative translation lookaside buffers (TLBs), two 4-ns 64-line tag RAMs, comparators, registers, and control logic. The TLB design contains a line encoder and valid bits with flash clear. Timing control allows read, write, associative accesses, and invalid search accesses with identical timings. The two caches time-share data input and sense amplifier circuits for improved density, and they are pipelined to allow a new access to start before the previous access is complete
Keywords :
buffer storage; content-addressable storage; integrated memory circuits; pipeline processing; storage management chips; 256 Kbit; 6 ns; 64-line tag RAMs; 7.7 ns; CAMMU; associative accesses; cache memory and memory management unit; comparators; control logic; flash clear; fully associative translation lookaside buffers; invalid search accesses; line encoder; pipelined caches; registers; sense amplifier circuits; Cache memory; Central Processing Unit; Circuits; Clocks; Logic; Memory management; Random access memory; Read-write memory; Registers; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
