Title :
An experimental DRAM with a NAND-structured cell
Author :
Hasegawa, Takehiro ; Takashima, Daisaburo ; Ogiwara, Ryu ; Ohta, Masako ; Shiratake, Shin-ichiro ; Hamamoto, Takeshi ; Yamada, Takashi ; Aoki, Masami ; Ishibashi, Shigeru ; Oowaki, Yukihito ; Watanabe, Shigeyoshi ; Masuoka, Fujio
Author_Institution :
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fDate :
11/1/1993 12:00:00 AM
Abstract :
An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm2, using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm2, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved
Keywords :
CMOS integrated circuits; DRAM chips; memory architecture; time division multiplexing; 0.4 mum; 112 ns; 256 Mbit; 30 ns; CMOS technology; DRAM; NAND-structured cell; access time; bit-line contact area; cell area per bit; chip area; die size; fast-block-access mode; isolation area; memory cells; random access mode; serial cycle time; time division multiplex sense-amplifier architecture; Area measurement; CMOS technology; Circuit synthesis; DRAM chips; Helium; Isolation technology; Nonhomogeneous media; Random access memory; Semiconductor device measurement; Semiconductor memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
