Subthreshold current reduction for decoded-driver by self-reverse biasing [DRAMs]

Author

Kawahara, Takayuki ; Horiguchi, Masashi ; Kawajiri, Yoshiki ; Kitsukawa, Goro ; Kure, Tokuo ; Aoki, Masakazu

Author_Institution

Central Res. Lab., Hitachi Ltd, Tokyo, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1136

Lastpage

1144

Abstract

Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM´s for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10 ^-3 in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25-μm technology

Keywords

CMOS integrated circuits; DRAM chips; delays; driver circuits; portable instruments; 0.25 mum; 1 ms; 1 ns; 250 to 350 K; 254 mV; CMOS technology; decoded-driver; delay time; high-speed DRAM; portable equipment; recovery time; self-reverse biasing; subthreshold current reduction; switching MOS transistor; test chip; transition time; Decoding; Delay effects; Driver circuits; MOSFETs; Power supplies; Subthreshold current; Switching circuits; Temperature distribution; Testing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245594

Filename

245594