DocumentCode
973647
Title
Low-Cost Gate Drive Circuit for Three-Level Neutral-Point-Clamped Voltage-Source Inverter
Author
Padilha, Felipe J C ; Suemitsu, Walter Issamu ; Bellar, Maria Dias ; Lourenco, Plutarcho Maravilha
Author_Institution
Electr. Power Res. Center, Rio de Janeiro
Volume
56
Issue
4
fYear
2009
fDate
4/1/2009 12:00:00 AM
Firstpage
1196
Lastpage
1204
Abstract
This paper presents a new hardware implementation of gate drive circuits applied to low-power neutral-point-clamped (NPC) multilevel three-phase inverters. The proposed circuit is based on commercially available MOS-gate driver ICs (MGDs) for large-scale applications, which may reduce the total cost of implementation of NPC inverters. Only one DC power supply is required to feed all the gate drivers for the three-phase system. Detailed design procedures are presented, which include the protection circuits for avoiding hazardous switching states of the power switches. Experimental results of a laboratory prototype demonstrate the validity of the proposed circuit. These results also suggest that for achieving safe operation of snubberless power switches during transients, a hybrid implementation of each NPC phase leg, consisting of MOSFETs with voltage ratings at half the DC bus voltage and of insulated gate bipolar transistors rated at the total DC bus voltage, is recommended.
Keywords
MOSFET circuits; driver circuits; invertors; power semiconductor switches; switching convertors; DC power supply; MOS-gate driver IC; MOSFET; protection circuits; snubberless power switches; three-level neutral-point-clamped voltage-source inverter; Charge pump technique; gate drive circuit; switch-voltage balancing; three-level neutral-point-clamped (NPC) inverter;
fLanguage
English
Journal_Title
Industrial Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0278-0046
Type
jour
DOI
10.1109/TIE.2008.2007554
Filename
4663830
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