Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g., AND-OR, NOR-NOR, NAND-NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it. We find that it also improves the efficiency of fault tolerance techniques as it significantly simplifies the designs. In addition, we found that it enables voting at nanoscale that can improve fault tolerance further. A nanoscale processor is implemented for evaluation purposes. We found that compared with an implementation on a Nanoscale Application-Specific IC (NASIC) fabric with one type of two-level logic, the density of this processor improves by up to 52% by using the heterogeneous logic. Furthermore, the yield is improved by 15% at 2% defective transistors and by 147% at 5% defect rates. Detailed analysis on density and yield is provided. The approach is applicable in grid-based fabrics in general, e.g., it can be used in both NASIC and hybrid semiconductor/nanowire/molecular (CMOL) designs.