The TInMANN VLSI chip

Author

Melton, Matthew S. ; Phan, Tan ; Reeves, Douglas S. ; Van den Bout, David E.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

3

Issue

3

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

375

Lastpage

384

Abstract

A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size. The neuron operates at a speed of 15 MHz, making it capable of processing 195000 three-dimensional training examples per second. Three man-months were required to synthesize the neuron and its associated level-sensitive scan logic using the OASIS silicon compiler. The ease of synthesis allowed many performance trade-offs to be examined, while the automatic testability features of the compiler helped the designers achieve 100% fault coverage of the chip. These factors served served to create a fast, dense, and reliable neural chip

Keywords

VLSI; circuit layout CAD; fault location; logic CAD; neural nets; parallel architectures; Kohonen self-organizing feature map; MOSIS TinyChip frame; OASIS silicon compiler; TInMANN; VLSI design; automatic testability features; fault coverage; level-sensitive scan logic; parallel architectures; stochastic architecture; Analog computers; Image coding; Logic; Network synthesis; Neural network hardware; Neural networks; Neurons; Stochastic processes; Vector quantization; Very large scale integration;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.129410

Filename

129410