A modular CMOS design of a Hamming network

A modular design approach for the CMOS implementation of a Hamming network is proposed. The Hamming network is an optimum minimum error classifier for binary patterns and is very suitable for a VLSI implementation due to its primarily feedforward structure. First, a modular chip that contains an array of N×M exclusive-NOR transconductors computes the matching scores between M encoded exemplar patterns (with N elements per exemplar) and an unknown input pattern. Then, a winner-take-all (WTA) circuit selects the exemplar pattern that most resembles the input pattern. By interconnecting multiple modular chips, the number and size of the patterns that can be stored in the network can be easily expanded. Measured experimental results are given to illustrate the performance and limitations of the hardware implementations of the Hamming network