Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Author

Jeng, Erik S. ; Chiu, Chia-Sung ; Hon, Chih-Hsueh ; Kuo, Pai-Chun ; Fan, Chen-Chia ; Hsieh, Chien-Sheng ; Hsu, Hui-Chun ; Chen, Yuan-Feng

Volume

54

Issue

12

fYear

2007

Firstpage

3299

Lastpage

3307

Abstract

This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance, are reported. Finally, the scalability of NOI devices is simulated and discussed.

Keywords

MOSFET; semiconductor storage; silicon compounds; SiN - Binary; charge retention; charge-trapping spacers; cycling endurance; nonoverlapped implantation nMOSFET; nonvolatile memories; silicon nitride spacers; voltage 0.8 V; CMOS technology; Dielectric devices; Intellectual property; MOSFETs; Nonvolatile memory; SONOS devices; Scalability; Silicon compounds; Threshold voltage; Tunneling; Charge trapping; nonoverlapped implantation (NOI); nonvolatile memory (NVM);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.908598

Filename

4383030