Parallel implementation of linear feedback shift registers for low power applications

The conventional implementation of shift registers systems such as linear feedback shift registers (LFSR) suffers from two major drawbacks: 1) all the elements in the structure are clocked during each clock cycle and 2) the throughput is limited to only one bit per clock cycle. Sequence generators implemented using this architecture dissipate a significant amount of power when clocked at high frequency. This is detrimental to the operation of low-power communication equipment and battery operated systems. This paper presents an architecture and an algorithm for the parallel implementation of digital sequences and shift register systems in general. The advantages of the parallel architecture are: 1) reduced power dissipation, and 2) higher throughput rate. However the implementation of sequence generators using this architecture requires a number of switches of the order of N (the length of the shift register) times M (the number of taps) between the register and the XOR tree making this implementation impractical. We present an algorithm which reduces this number to the order of N+M thus making this approach practical. The parallel architecture is characterized by its flexibility to provide more than one bit of output with the accompanying advantage of operating with a higher throughput at a lower clock rate to further reduce the power dissipation