The relationship between gate bias and hot-carrier-induced instabilities in buried- and surface-channel PMOSFETs

For accurate predictions of device reliability with respect to hot-carrier effects, it is necessary to establish worst-case stress bias conditions. Detailed measurements of hot-carrier-induced instabilities in short-channel PMOSFETs have revealed that stress gate bias conditions corresponding to peak gate currents result in maximum shifts in device parameters. However, for some parameters, notably those measured at low drain bias, comparable shifts are observed for stress gate bias conditions that correspond to peak substrate currents. These observations are valid for both buried-channel (n-type polysilicon gate) and surface-channel (p-type polysilicon gate) PMOSFETs. An interpretation of these results based on the generation of tapped oxide charge and interface traps is proposed