Design of a DPCM codec for VLSI realization in CMOS technology

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.