DocumentCode
975147
Title
Planar normally-off GaAs JFET for high speed logic circuits
Author
Kato, Yu ; Dohsen, M. ; Kasahara, J. ; Taira, K. ; Watanabe, N.
Author_Institution
Sony Corporation, Research Center, Yokohama, Japan
Volume
17
Issue
25
fYear
1981
Firstpage
951
Lastpage
952
Abstract
Normally-off JFETs with 1.3 ¿m-long gates were fabricated by selective double ion implantation for the n and n+ regions and selective Zn diffusion for the p-gate area. A JFET with a 10 ¿m-wide gate had a transconductance of 2 mS in average and a high value of 3 mS. A 15 stage ring oscillator made of resistively loaded DCFLs showed the minimum delay time of 45 ps, the shortest value obtained based on optical lithography. The minimum power-delay product was 3.8 fJ with a delay time of 83 ps.
Keywords
III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated logic circuits; junction gate field effect transistors; 15 stage ring oscillator; III-V semiconductor; delay time; high speed logic circuits; optical lithography; planar normally-off GaAs JFET; selective Zn diffusion; selective double ion implantation; transconductance;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19810665
Filename
4246149
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