• DocumentCode
    975633
  • Title

    Cache write generate for parallel image processing on shared memory architectures

  • Author

    Wittenbrink, Craig M. ; Somani, Arun K. ; Chen, Chung-Ho

  • Volume
    5
  • Issue
    7
  • fYear
    1996
  • fDate
    7/1/1996 12:00:00 AM
  • Firstpage
    1204
  • Lastpage
    1208
  • Abstract
    We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated
  • Keywords
    cache storage; image processing; parallel processing; shared memory systems; CPU efficiency; UW-Proteus system; cache hits; cache latency; cache mode; cache write generate; main memory bandwidth; parallel image processing; processor configurations; register level simulations; shared memory architectures; Bandwidth; Delay; Hardware design languages; Image generation; Image processing; Image segmentation; Measurement; Memory architecture; Read-write memory; Registers;
  • fLanguage
    English
  • Journal_Title
    Image Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7149
  • Type

    jour

  • DOI
    10.1109/83.502410
  • Filename
    502410
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=975633