Title :
Cache write generate for parallel image processing on shared memory architectures
Author :
Wittenbrink, Craig M. ; Somani, Arun K. ; Chen, Chung-Ho
fDate :
7/1/1996 12:00:00 AM
Abstract :
We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated
Keywords :
cache storage; image processing; parallel processing; shared memory systems; CPU efficiency; UW-Proteus system; cache hits; cache latency; cache mode; cache write generate; main memory bandwidth; parallel image processing; processor configurations; register level simulations; shared memory architectures; Bandwidth; Delay; Hardware design languages; Image generation; Image processing; Image segmentation; Measurement; Memory architecture; Read-write memory; Registers;
Journal_Title :
Image Processing, IEEE Transactions on
