Criteria for setting the width of CCD front end transistor to reach minimum pixel noise

The paper gives the criteria to calculate the width of the front end transistor integrated next to the charge sensing electrode of CCDs or, in general, of semiconductor detectors, in order to reach the minimum noise in the readout of the signal charge. It accounts for white, series and parallel, and 1/f noise contributions. In addition, it points out two different design criteria depending whether a JFET or a MOSFET is used. The attention given to the JFET is due to a lower 1/f noise component, which makes these transistors more appealing as input devices in very high resolution detectors. The paper shows that there is a characteristic width of the FET gate that practically does not depend on the noise sources but depends only on the capacitance seen by the charge sensing electrode of the detector, making possible the optimum design of the transistor prior to knowledge of the real values of the spectral density of the noise sources, which are usually precisely known only at the end of the fabrication process. The paper shows that the pixel noise raises sharply as the transistor gate width departs from its optimum value