Title :
A self-aligned counter-doped well process utilizing channeling ion implantation
Author :
Nakamura, Hiroyuki ; Horiuchi, Tadahiko
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
fDate :
7/1/1996 12:00:00 AM
Abstract :
This paper describes a new self-aligned counter-doped well process realizing low junction capacitance CMOS´s. This technology intentionally utilizes channeling ion implantation to achieve counter doping of the well in the same mask step as SD implantation. The benefit of this technology is its process simplicity with full compatibility with the conventional CMOS process. Applying this technology to a 0.25-μm CMOS process, a 50%-70% reduction in junction capacitance is achieved, and an 18.3% improvement in simulated propagation delay time is demonstrated for 0.25-μm CMOS inverter chains under 0.9-V operation
Keywords :
CMOS integrated circuits; MOSFET; ULSI; capacitance; channelling; doping profiles; ion implantation; secondary ion mass spectra; 0.25 mum; 0.25-μm CMOS process; 0.9 V; CMOS inverter chains; MOSFET fabrication; SD implantation; SIMS profiles; Si:B; Si:P; channeling ion implantation; junction capacitance reduction; low junction capacitance CMOS; low power ULSI; mask step; propagation delay time; self-aligned counter-doped well process; CMOS process; CMOS technology; Costs; Counting circuits; Doping; Electrodes; Fabrication; Impurities; Ion implantation; Parasitic capacitance;
Journal_Title :
Electron Devices, IEEE Transactions on
