JFET/SOS devices. I. Transistor characteristics and modeling results

Author

Halle, Linda F. ; Knudsen, John F.

Author_Institution

Aerosp. Corp., Los Angeles, CA, USA

Volume

35

Issue

3

fYear

1988

fDate

3/1/1988 12:00:00 AM

Firstpage

353

Lastpage

358

Abstract

A process for fabricating n-channel junction field-effect transistors (JFET) on silicon-on-sapphire (SOS) wafers has been developed. Both enhancement-mode and depletion-mode transistors were fabricated, and their characteristics were measured and are discussed. All dopants were ion implanted. A number of calculational tools, including SUPREME-II, were used to estimate the junction depths and the mode of device operation. Calculations were also performed using PISCES-II, a device-modeling program that predicts operating characteristics. The mobilities used in these calculations were reduced from bulk silicon values to account for the degraded mobility of the SOS material. The mobility of the SOS material was measured using capacitance-voltage and conductance-voltage techniques on a device with a long gate. A decrease in mobility with decreasing temperature is deduced from device behavior at low temperatures

Keywords

carrier mobility; ion implantation; junction gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; C-V techniques; PISCES-II; SOS JFETs; SUPREME-II; Si-Al₂O₃; conductance-voltage techniques; depletion-mode transistors; enhancement mode transistors; fabrication; ion implantation; junction depths; mobilities; modeling; operational mode; Circuits; Conducting materials; FETs; Fabrication; Implants; MOSFETs; Semiconductor device modeling; Semiconductor materials; Semiconductor process modeling; Silicon;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.2461

Filename

2461