DocumentCode :
975825
Title :
Serial Addition: Locally Connected Architectures
Author :
Beiu, Valeriu ; Aunet, Snorre ; Nyathi, Jabulani ; Rydberg, Robert R., III ; Ibrahim, Walid
Author_Institution :
United Arab Emirates Univ., Al Ain
Volume :
54
Issue :
11
fYear :
2007
Firstpage :
2564
Lastpage :
2579
Abstract :
This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOS-based examples for addition starting from the device level and moving up to the gate, the circuit, and the block level. Our analysis, backed by simulation results, on comparing parallel and serial addition shows that serial adders are more reliable while also dissipating less. Their reliability can be improved by using reliability-enhanced gates and/or other redundancy techniques (like e.g., multiplexing). Additionally, the architectural technique of short-circuiting the outputs (of several redundant devices/gates/blocks) exhibits "vanishing" voting and an inherent fault detection mechanism, as both transient and permanent faults could be detected based on current changes. The choice of CMOS is due to the broad design base available (but the ideas can be applied to other technologies), while addition was chosen due to its very solid background (both theoretical and practical). The design approach will constantly be geared towards enhancing reliability as much as possible at all the levels. Theory and simulations will support the claim that a serial adder is a very serious candidate for highly reliable and low power operations. Finally, our simulations will identify the VDD range where the power-delay-product and energy-delay-product are minimized. All of these suggest that a reliable (redundant) solution can also be a low power one if using serial architectures, while speed could still be traded for power (e.g., by dynamically varying the supply voltage both above and below Vth).
Keywords :
adders; digital arithmetic; integrated circuit reliability; nanoelectronics; reviews; CMOS; circuit reliability; locally connected architectures; nanoelectronic challenges; parallel addition; serial addition; Adders; Analytical models; CMOS technology; Circuit faults; Circuit simulation; Fault detection; Redundancy; Reliability theory; Solids; Voting; Addition; fault/defect tolerance; multiplexing; nanoarchitectures; reliability; serial architectures;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2007.907885
Filename :
4383232
Link To Document :
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