CMOS design of chaotic oscillators using state variables: a monolithic Chua´s circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS´s, PWL VCCS´s, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS´s and PWL VCCS´s are presented and applied to design a Chua´s circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua´s circuit prototype are given. The prototype has been fabricated in a 2.4-μm double-poly n-well CMOS technology, and occupies 0.35 mm², with a power consumption of 1.6 mW for a ±2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua´s attractor by changing a bias current