Title :
A speed-enhanced DRAM array architecture with embedded ECC
Author :
Arimoto, Kazutami ; Matsuda, Yoshio ; Furutani, Kiyohiro ; Tsukude, Masaki ; Ooishi, Tsukasa ; Mashiko, Koichiro ; Fujishima, Kazuyasu
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fDate :
2/1/1990 12:00:00 AM
Abstract :
An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance
Keywords :
MOS integrated circuits; VLSI; error correction; integrated circuit technology; integrated memory circuits; random-access storage; 16 Mbit; ULSI; array-embedded error checking and correcting; countermeasures for small signal charge; embedded ECC; hierarchical data bus configuration; high-speed array access; multipurpose register; page mode; scaling down; speed-enhanced DRAM array architecture; Decoding; Delay effects; Error correction codes; Helium; Maintenance; Parasitic capacitance; Random access memory; Registers; Timing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
