Title :
Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs
Author :
Yamasaki, Kazuhiko ; Asai, Kikuo ; Mizutani, Tomoko ; Kurumada, K.
Author_Institution :
NTT, Musashino Electrical Communication Laboratory, Musashino, Japan
Abstract :
A new GaAs MESFET structure with n+-implanted layers and a self-aligned gate has been developed by dielectric lift-off technology with trilevel resist. The electrical characteristics are improved greatly by resistance reduction outside the channel under the gate. 280 mS/mm transconductance and 39.5 ps/gate propagation delay have been obtained.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; ion implantation; 280 mS/mm transconductance; 39.5 ps/gate propagation delay; GaAs MESFET structure; III-V semiconductor; dielectric lift-off technology; electrical characteristics; n+-layer technology; self-aligned implantation; trilevel resist;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19820080
