A multibit test trigger circuit for megabit SRAMs

Author

Miyaji, Fumio ; Emori, Takashi ; Matsuyama, Yasushi ; Kanaishi, Yoshikazu ; Seno, Katsunori ; Hagiwara, Yoshiaki

Author_Institution

Sony Corp., Atsugi, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

68

Lastpage

71

Abstract

A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC pins is especially effective as a 4-Mb SRAM. In addition, the proposed scheme is able to act as a logic trigger for an MBT circuit. The scheme is simple and effective. The logic trigger mode is proposed for future standardization

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; integrated memory circuits; random-access storage; 4 Mbit; DFT; design for testability; features; logic trigger mode; megabit SRAMs; multibit test trigger circuit; trigger mode selection; use of counter circuits; Circuit testing; Conductors; Counting circuits; Flip-flops; Logic circuits; Packaging; Pins; Random access memory; Research and development; Trigger circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50286

Filename

50286