Title :
A high-speed parallel sensing architecture for multi-megabit flash E2PROMs
Author :
Kobayashi, Kazuo ; Nakayama, Takeshi ; Miyawaki, Yoshikazu ; Hayashikoshi, Masanori ; Terada, Yasushi ; Yoshihara, Tsutomu
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fDate :
2/1/1990 12:00:00 AM
Abstract :
A high-speed parallel sensing architecture for high-density 5-V-only flash E2PROMs is described. A source-biasing technique enhanced the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10-μA cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size
Keywords :
EPROM; MOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; 10 muA; 40 ns; 5 V; 5-V-only; ULSI; cell current; chip size; column latch; differential sense amplifiers; flash E2PROMs; high-density; high-speed parallel sensing architecture; multi-megabit; program mode; source-biasing technique; stable sensing; Clocks; Differential amplifiers; Electrons; Equivalent circuits; Latches; Nonvolatile memory; PROM; Timing; Tunneling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
