Title :
High-performance BiCMOS 100 K-gate array
Author :
Gall, James D. ; Yee, Ah-Lyan ; Chau, Kwok Kit ; Wang, I. Fay ; Davis, Harvey ; Swamy, Shobana ; Nguyen, Van M. ; Ruparel, Kamalesh Natvarlal ; Moore, Kermit ; Chae, Brian ; Lemonds, Carl E., Jr. ; Eyres, Pat ; Yoshino, Toshiaki ; Shah, Ashwin H.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
2/1/1990 12:00:00 AM
Abstract :
A BiCMOS gate array in 0.8-μm technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106 K-gate array has been built on a 1.14-cm2 chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90%. The gate array was used to implement a 74 K-gate filter design with testability features such as JTAG and two-phase scan
Keywords :
BIMOS integrated circuits; VLSI; integrated circuit technology; logic arrays; 0.8 micron; 100 to 217 ps; BIST; BiCMOS; CMOS intrinsic gate delays; ECL I/O capability; ECL compatibility; JTAG; VLSI; array utilization; base cell; design for testability; digital filter design; filter design; full bipolar drive capability; gate array; intrinsic delays; large-arrayed macros; multipliers; primitive gates; register files; testability features; three levels of metal; two-phase scan; BiCMOS integrated circuits; CMOS technology; Capacitance; Circuit testing; Delay; Filters; Inverters; Paper technology; Registers; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
