CMOS subnanosecond true-ECL output buffer

Author

Schumacher, Hans-JÜrgen ; Dikken, Jan ; Seevinck, Evert

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

150

Lastpage

154

Abstract

An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented

Keywords

CMOS integrated circuits; buffer circuits; emitter-coupled logic; 0.9 ns; CMOS buffer circuit; ECL 100 K compatible output buffer; ECL output buffer; Si; capacitive loading; circuit layout; circuit technique; error correction; implementation; negative feedback; output buffer circuit; practical aspects; simulation results; technology features; CMOS logic circuits; Circuit simulation; Circuit stability; Coupling circuits; Delay; Error correction; Logic circuits; Negative feedback; Power supplies; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50297

Filename

50297