A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

Author

Suzaki, M. ; Yamanaka, Naoaki ; Hirata, Michihiro ; Kikuchi, Shiro

Author_Institution

NTT Corp., Kanagawa, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

155

Lastpage

159

Abstract

An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI

Keywords

ISDN; bipolar integrated circuits; digital integrated circuits; electronic switching systems; elemental semiconductors; emitter-coupled logic; large scale integration; semiconductor switches; silicon; -2 V; -4 V; 0.9 W; 16×16 crosspoint switch; 2 to 2.5 Gbit/s; 2.8 W; 8×8 crosspoint switch; B-ISDN; ECL-compatible interface; HDTV signals; LSIs; SST-1A; Si; bipolar crosspoint switch; bit error rate; broadband ISDN; circuit design; crosspoint switch LSI; differential CML cell; power dissipation; pseudorandom NRZ sequence; pulse jitter; semiconductors; small internal voltage swing; super self-aligned process technology; Bit error rate; Circuit synthesis; Jitter; Large scale integration; Optical signal processing; Power supplies; Pulsed power supplies; Switches; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50298

Filename

50298