Title :
Implementation issues of the ATM cell delineation mechanism
Author :
Antonakopoulos, Theodore ; Makios, V.
fDate :
5/23/1996 12:00:00 AM
Abstract :
The cell delineation mechanism (CDM) used in the asynchronous transfer mode (ATM) interfaces is based on the validation of the header error control (HEC) byte of the incoming cells, and is used for extracting the boundaries of the incoming cell stream. The CDM is analysed and an efficient implementation algorithm is derived, resulting in a hardware architecture, applicable at high data rates
Keywords :
B-ISDN; SONET; asynchronous transfer mode; data communication; field programmable gate arrays; ATM cell delineation mechanism; ATM interfaces; FPGA implementation; asynchronous transfer mode; cell stream boundaries extraction; hardware architecture; header error control byte; high data rates; implementation algorithm; incoming cell stream; incoming cells;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960631
