DocumentCode
978719
Title
IDDQ test invalidation by break faults
Author
Dalpasso, Marcello ; Favalli, Michele ; Olivo, Piero
Author_Institution
Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ.
Volume
32
Issue
11
fYear
1996
fDate
5/23/1996 12:00:00 AM
Firstpage
994
Lastpage
995
Abstract
The effectiveness of IDDQ testing for bridging faults in CMOS ICs can be decreased if break faults are present in the circuit. The robustness to such invalidation is investigated here, leading to claims for a better test pattern generation for IDDQ testing. As for the proposed solution, test vectors that activate a larger number of different current paths can build a more robust test sequence
Keywords
CMOS integrated circuits; fault diagnosis; integrated circuit testing; CMOS ICs; IDDQ testing; break faults; bridging faults; invalidation robustness; quiescent power-supply current monitoring; test pattern generation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960626
Filename
503076
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