Title :
Design of a low-power 32 K CMOS programmable delay-line memory
Author :
Dejhan, Kobchai ; Demassieux, Nicolas ; Colavin, Oswald ; Galisson, Arnaud ; Artieri, Alain ; Jutand, Francis
Author_Institution :
Ecole Nat. Superieure des Telecommun., Paris, France
fDate :
2/1/1990 12:00:00 AM
Abstract :
A design of a programmable digital delay based on shift registers in 1.2-μm CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1025-pixel×8-b delay lines. An integrable circuit technique for decreasing the power dissipation of the shift register is also suggested
Keywords :
CMOS integrated circuits; delay lines; integrated memory circuits; shift registers; 1.2 micron; 20 MHz; 200 mW; 32 kbit; CMOS technology; integrable circuit technique; power dissipation; programmable delay-line memory; shift registers; variable length delay characteristics; CMOS technology; Circuits; Delay lines; Frequency conversion; Image sampling; Power dissipation; Random access memory; Read-write memory; Shift registers; Strontium;
Journal_Title :
Solid-State Circuits, IEEE Journal of
