Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector

For a single-loop frequency synthesiser, there is a trade-off between time-to-lock and output phase-noise. To lock a PLL quickly, a high natural frequency (ω_n) is required, while a low ω_n is necessary to obtain good jitter damping. The author presents a technique to reduce the time to lock of a frequency synthesiser PLL without changing the jitter transfer function