A 6-F/sup 2/ bit cell design based on one transistor and two uneven magnetic tunnel junctions structure and low power design for MRAM

Author

Hung, Chien-Chung ; Kao, Ming-Jer ; Chen, Young-Shying ; Wang, Yung-Hung ; Lee, Yuan-Jen ; Chen, Wei-Chuan ; Lin, Wen-Chin ; Shen, Kuei-Hung ; Chen, Kuo-Lung ; Chao, Shiuh ; Tang, Denny Duan-Lee ; Tsai, Ming-Jinn

Author_Institution

Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsinchu

Volume

53

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

1530

Lastpage

1538

Abstract

Novel cell structures based on one transistor and two uneven magnetic tunnel junction cell and pillar write word line architecture are proposed to shrink the bit size with a potential down to 6 F² by a so-called extended via process, and to reduce the writing current by a factor of 2, combined with the nature of nonvolatility and high speed, making the magnetoresistive random access memory suitable for universal memory applications

Keywords

low-power electronics; magnetic storage; magnetic tunnelling; magnetoresistive devices; random-access storage; MRAM device; cell design; low power design; magnetic memories; magnetic tunnel junctions; magnetoresistive devices; magnetoresistive random access memory; pillar write word line; Chaos; Electronics industry; Industrial electronics; Magnetic memory; Magnetic tunneling; Magnetoresistive devices; Random access memory; Scalability; Transistors; Tunneling magnetoresistance; High density; low power; magnetic memories; magnetic tunnel junction (MTJ); magnetoresistive devices; magnetoresistive random access memory (MRAM);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.876286

Filename

1643484