Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.