DocumentCode
979060
Title
Characteristics of an address discharge time lag in terms of a wall voltage in an AC PDP
Author
Shin, Bhum Jae
Author_Institution
Dept. of Electron. Eng., Sejong Univ., Seoul
Volume
53
Issue
7
fYear
2006
fDate
7/1/2006 12:00:00 AM
Firstpage
1539
Lastpage
1542
Abstract
The characteristics of an address discharge have been investigated in terms of a wall voltage, which plays an important role in achieving a high-speed address discharge in an ac plasma display panel. The wall-voltage conditions generated in a reset period are a considerable factor to reduce the address-discharge time lag. Based on the experimental results, the reset driving scheme in which an address bias voltage is applied to the address electrode in a reset period is proposed to enhance the characteristics of an address-discharge time lag
Keywords
discharges (electric); driver circuits; plasma displays; AC PDP; AC plasma display panel; address bias voltage; address discharge time lag; reset driving; wall voltage; AC generators; Breakdown voltage; Electrodes; Graphics; HDTV; High definition video; Image quality; Plasma displays; TV; Testing; AC plasma display panel (PDP); address-discharge time lag; wall voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2006.876038
Filename
1643485
Link To Document