Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si_1-xGe_x S/D) technology. Experimental results on Si_1-xGe_x S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si_1-xGe_x is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si_1-x Ge_x and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si_1-xGe _x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes