• DocumentCode
    980490
  • Title

    Optimal folding of bit sliced stacks

  • Author

    Paik, Doowon ; Sahni, Sartaj

  • Author_Institution
    AT&T Bell Labs., Murray Hill, NJ, USA
  • Volume
    12
  • Issue
    11
  • fYear
    1993
  • fDate
    11/1/1993 12:00:00 AM
  • Firstpage
    1679
  • Lastpage
    1685
  • Abstract
    We develop polynomial time algorithms to optimally fold stacked bit sliced architectures to minimize area subject to height or width constraints. These algorithms may also be applied to folding problems that arise in standard cell and sea-of-gates designs
  • Keywords
    circuit layout CAD; logic CAD; network routing; CAD; SOG design; bit sliced architectures; bit sliced stacks; height constraints; polynomial time algorithms; sea-of-gates designs; standard cell; width constraints; Algorithm design and analysis; CMOS technology; Circuits; Design optimization; Polynomials; Routing; Space technology; Wires;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.248078
  • Filename
    248078
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=980490