Generic DFT approach for pattern sensitive faults in word-oriented memories

Author

Amin, A.A. ; Hamzah, A.A. ; Abdel-Aal, R.E.

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

Volume

143

Issue

3

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

199

Lastpage

202

Abstract

The testability problem of word-oriented memories (WOMs) for pattern sensitive faults is addressed. A novel design for testability (DFT) strategy allows efficient built-in self-testing (BIST) of WOMs. By proper selection of the memory array tiling scheme, it is possible to implement O(√n) BIST algorithms which test WOMs for various types of neighbourhood pattern sensitive faults (NPSFs). The inputs of the column decoders are modified to allow parallel writing into multiple words, and coincidence comparators are added to allow parallel verification of row data with minimal effect on chip area and performance

Keywords

built-in self test; design for testability; integrated circuit testing; integrated memory circuits; random-access storage; built-in self-testing; chip area; coincidence comparators; column decoders; design for testability; generic DFT approach; memory array tiling scheme; neighbourhood pattern sensitive faults; pattern sensitive faults; performance; testability problem; word-oriented memories;

fLanguage

English

Journal_Title

Computers and Digital Techniques, IEE Proceedings -

Publisher

iet

ISSN

1350-2387

Type

jour

DOI

10.1049/ip-cdt:19960334

Filename

503292