DocumentCode
980678
Title
Image processing using one-dimensional processor arrays
Author
Hammerstrom, Dan W. ; Lulich, Daniel P.
Author_Institution
Adaptive Solutions Inc., Beaverton, OR, USA
Volume
84
Issue
7
fYear
1996
fDate
7/1/1996 12:00:00 AM
Firstpage
1005
Lastpage
1018
Abstract
The first half of this paper presents the design rationale for CNAPS, a specialized one-dimensional (1-D) processor array developed by Adaptive Solutions Inc. In this context, we discuss the problem of Amdahl´s law which severely constrains special-purpose architectures. We also discuss specific architectural decisions such as the kind of parallelism, the computational precision of the processors, on-chip versus off-chip processor memory, and-most importantly-the interprocessor communication architecture. We argue that, for our particular set of applications, a 1-D architecture gives the best “bang for the buck”, even when compared to the more traditional two-dimensional (2-D) architecture. The second half of this paper describes how several simple algorithms map to the CNAPS array. Our results show that the CNAPS 1-D array offers excellent performance over a range of IP algorithms. We also briefly look at the performance of CNAPS as a pattern recognition engine because many image processing and pattern recognition problems are intimately related
Keywords
image processing; multiprocessing systems; parallel architectures; Adaptive Solutions; Amdahl law; CNAPS; IP algorithms; computational precision; image processing; interprocessor communication; one-dimensional processor array; parallel architecture; pattern recognition engine; processor memory; Application software; Circuits; Computer architecture; Concurrent computing; Desktop publishing; Image processing; Parallel processing; Pattern recognition; Silicon; Very large scale integration;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/5.503300
Filename
503300
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