Title :
Physical register reference counting
Author_Institution :
Dept. of Comput. & Inf. Sci., Univ. of Pennsylvania, Philadelphia, PA
Abstract :
Several proposed techniques including CPR (checkpoint processing and recovery) and NoSQ (no store queue) rely on reference counting to manage physical registers. However, the register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.
Keywords :
checkpointing; shift registers; binary representations; checkpoint processing; matrices; no store queue; physical register reference counting; recovery technique; Counting circuits; Engines; Information science; Microarchitecture; Physics computing; Proposals; Registers; Micro-architecture implementation considerations; Superscalar; and statically-scheduled implementation; dynamically-scheduled; dynamically-scheduled and statically-scheduled implementation;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2007.15