Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology

Author

Hsu, Heng-Ming ; Chan, Kai-Yuen ; Chien, Hung-Chi ; Kuan, Han-Chien

Author_Institution

Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung

Volume

55

Issue

11

fYear

2008

Firstpage

3208

Lastpage

3213

Abstract

A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high-Q inductor for RFIC applications.

Keywords

CMOS integrated circuits; VLSI; inductors; radiofrequency integrated circuits; CMOS technology; VLSI technology; analytical design algorithm; minimum metal resistance; on-chip inductors; planar inductor layout; radio-frequency integrated circuit applications; size 90 nm; variable-width inductor; Algorithm design and analysis; CMOS technology; Coils; Inductance; Inductors; Low-noise amplifiers; Radio frequency; Radiofrequency integrated circuits; Silicon; Voltage-controlled oscillators; Analytical algorithm; minimum resistance; on-chip inductor; variable width;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2008.2004248

Filename

4668566