Title :
A BIST Circuit for DLL Fault Detection
Author :
Jia, Cheng ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
Abstract :
A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple XNOR logic gate and uncalibrated delay lines to sample the output of the XNOR gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the ldquostart testrdquo signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.
Keywords :
VLSI; built-in self test; delay lines; delay lock loops; fault simulation; logic circuits; logic gates; BIST circuit; DLL fault detection; VLSI; XNOR logic gate; analog DLL; built-in-self-test circuit; delay-locked loop circuit; fault coverage; fault simulation; structural faults; uncalibrated delay lines; very large scale integration system; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Delay; Electrical fault detection; Jitter; Performance evaluation; Voltage; Analog test; built-in self test (BIST); delay locked loop (DLL); fault detection; mixed signal test;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2001732
