Title :
SIERRA: a 3-D device simulator for reliability modeling
Author :
Chern, Jue-Hsien ; Maeda, John T. ; Arledge, Lawrence A., Jr. ; Yang, Ping
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
5/1/1989 12:00:00 AM
Abstract :
SIERRA is a 3-D general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under DC, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5× to 7× speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and DRAM (dynamic random-access memory) single-event-upset studies is described
Keywords :
CMOS integrated circuits; digital simulation; electronic engineering computing; random-access storage; reliability; semiconductor device models; 3-D device simulator; DC conditions; DRAM SEV studies; IC device modelling; ILU-CGS method; Poisson equations; SIERRA; continuity equations; convergence rate; coupled Poisson and continuity equations; general-purpose semiconductor-device simulation program; incomplete LU; matrix solver; memory size; parasitic CMOS latchup; preconditioned conjugate gradient square; reliability issues; reliability modeling; reliability-oriented simulations; small-signal conditions; speedup; transient conditions; transient problems; vector/parallel minisupercomputer; Circuit simulation; Convergence; Instruments; Integrated circuit modeling; Poisson equations; Semiconductor device modeling; Semiconductor device reliability; Semiconductor devices; Silicon; Single event upset;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on