Title :
A heuristic algorithm for ordering the columns in one-dimensional logica arrays
Author :
Hong, Youn-Sik ; Park, Kyu-Ho ; Kim, Myunghwan
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
5/1/1989 12:00:00 AM
Abstract :
The authors focus on the ordering of the columns to minimize the necessary number of tracks in one-dimensional logic array. They use a column-orientation approach to this problem. Each net is converted into a complete graph (or clique). The weighted graph using such topological transformation is unique. The necessary number of tracks can be evaluated by the cut of the two seeds of orderings, the left seed vertex and the right seed vertex. The authors find the minimal track assignments by minimizing the cut of the seed vertex. Additionally, a useful concept called the overriding property is introduced. It determines the local optimal assignments for two or more columns with the above property. The author´s algorithm works well with either a uni- or bidirectional approach to select the seed of ordering. Results obtained by the proposed algorithm and the simulated annealing approach are compared
Keywords :
circuit layout CAD; logic arrays; bidirectional approach; column-orientation approach; complete graph; heuristic algorithm; left seed vertex; local optimal assignments; minimizing; necessary number of tracks; number of tracks minimization; one-dimensional logica arrays; ordering of columns; overriding property; right seed vertex; simulated annealing; topological transformation; track assignments; undirectional approach; weighted graph; Adders; CMOS logic circuits; CMOS technology; Heuristic algorithms; Logic arrays; Logic design; MOS devices; Simulated annealing; Wire; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on