Title :
Activity-sensitive architectural power analysis
Author :
Landman, Paul E. ; Rabaey, Jan M.
Author_Institution :
DSP R&d Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
6/1/1996 12:00:00 AM
Abstract :
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criterion. As such there is a growing need for tools that can accurately predict power consumption early in the design process, many high-level power analysis models do not adequately model activity, however, leading to inaccurate results. This paper describes an activity-sensitive power analysis strategy for datapath, memory, control path, and interconnect elements. Since datapath and memory modeling has been described in a previous publication, this paper focuses mainly on a new Activity-Based Control (ABC) model and on a hierarchical interconnect analysis strategy that enables estimates of chip area as well as power consumption. Architecture-level estimates are compared to switch-level measurements based on net lists extracted from the layouts of three chips: a digital filter, a global controller, and a microprocessor. The average power estimation error is about 9% with a standard deviation of 10%, and the area estimates err on average by 14% with a standard deviation of 6%
Keywords :
circuit analysis computing; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; SPA tool; activity-based control model; activity-sensitive architectural power analysis; chip area esimation; critical design criterion; hierarchical interconnect analysis strategy; power consumption; Data analysis; Digital filters; Electronics industry; Electronics packaging; Energy consumption; Estimation error; Microprocessors; Predictive models; Process design; Semiconductor device measurement;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on