DocumentCode
984436
Title
Permissible functions for multioutput components in combinational logic optimization
Author
Watanabe, Yosinori ; Guerra, Lisa M. ; Brayton, Robert K.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
Volume
15
Issue
7
fYear
1996
fDate
7/1/1996 12:00:00 AM
Firstpage
732
Lastpage
744
Abstract
This paper is concerned with logic optimization of multilevel combinational logic circuits. In the light of theoretical work of the past years, where a circuit is modeled by a Boolean network in which each node implements a single-output Boolean function, we address how a concurrent optimization over multiple nodes or components can lead to further optimization compared to conventional minimization techniques. In particular, we provide a procedure for computing maximally compatible sets of permissible relations for multiple nodes. This is a generalization of the classical notion of a compatible set of permissible functions for a single node, where no method is known for correctly computing such a maximal set. We provide a method for computing the set correctly for the general case. Based on this, we develop and implement a procedure for optimizing multiple nodes concurrently. The proposed procedure has been implemented, and we present experimental results
Keywords
Boolean functions; circuit CAD; circuit optimisation; combinational circuits; logic CAD; multivalued logic circuits; set theory; Boolean network; combinational logic optimization; concurrent optimization; maximally compatible sets; multilevel combinational logic circuits; multioutput components; multiple nodes; permissible functions; Boolean functions; Circuit synthesis; Combinational circuits; Computer networks; Logic circuits; Minimization; Programmable logic arrays;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.503942
Filename
503942
Link To Document