DocumentCode :
984483
Title :
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Author :
Collins, Rebecca L. ; Carloni, Luca P.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY
Volume :
27
Issue :
12
fYear :
2008
Firstpage :
2277
Lastpage :
2290
Abstract :
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while following the synchronous design paradigm. In a latency-insensitive system (LIS), each core is encapsulated within a shell, which is a synthesized interface module that dynamically controls its operation. At each clock period, if new data have not arrived on an input channel or if a stalling request has arrived on an output channel, the shell stalls the core and buffers other incoming valid data for future processing. The combination of finite buffers and backpressure from stalling can cause throughput degradation. Previous works addressed this problem by increasing buffer space to reduce the backpressure requests or inserting extra buffering to balance the channel latency around a LIS. We explore the theoretical complexity of these approaches and propose a heuristic algorithm for efficient queue sizing (QS). We evaluate the heuristic algorithm with experiments over a large set of synthetically generated systems and with a case study of a real SoC system. We find that the topology of a LIS can impact not only how much throughput degradation will occur but also the difficulty of finding optimal QS solutions.
Keywords :
network synthesis; network topology; protocols; system-on-chip; SoC system; channel latency; intercore communication channels; latency-insensitive systems; queue sizing; system-on-chip; topology-based performance analysis; Communication channels; Control system synthesis; Degradation; Design engineering; Heuristic algorithms; Performance analysis; Protocols; System-on-a-chip; Systems engineering and theory; Throughput; Latency-insensitive design (LID); performance analysis; system-level design; systems-on-chip (SoCs);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.2008914
Filename :
4670069
Link To Document :
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