DocumentCode
984550
Title
Sub-fJ inverter analysis for GaAs VLSI
Author
Togashi, Minoru ; Ino, M. ; Hirayama, Motoko
Author_Institution
NTT, Musashino Electrical Communication Laboratory, Musashino, Japan
Volume
19
Issue
6
fYear
1983
Firstpage
231
Lastpage
232
Abstract
An E-D GaAs inverter in the low supply voltage region was analysed to obtain small energy operation. The optimum values for the switching FET threshold voltage and an average load current at a supply voltage VDD = 0.4 V are 0.2 V and half of an average on-current for the switching FET, respectively. Following this analytical design, 15-stage ring oscillators were fabricated and a minimum value for the product of inverter power dissipation and inverter switching time Pdistpd of 0.75 fJ was obtained.
Keywords
III-V semiconductors; field effect integrated circuits; integrated logic circuits; large scale integration; semiconductor device models; 0.75 fJ invertor analysis; 15-stage ring oscillators; DCFL circuits; E-D GaAs inverter; GaAs VLSI; MESFET; average load current; logic circuits; low supply voltage region; model; power dissipation; small energy operation; switching FET threshold voltage; switching time;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19830159
Filename
4247534
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