A built-in self-repair design for RAMs with 2-D redundancy

Author

Li, Jin-Fu ; Yeh, Jen-Chieh ; Huang, Rei-Fu ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan

Volume

13

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

742

Lastpage

745

Abstract

This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K /spl times/ 64 SRAM.

Keywords

built-in self test; embedded systems; integrated circuit testing; random-access storage; redundancy; 2D redundancy; RAM; built-in redundancy analysis; built-in self-repair design; built-in self-test; embedded memories; random access memory; semiconductor memories; Algorithm design and analysis; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Random access memory; Read-write memory; Redundancy; Semiconductor memory; Built-in redundancy analysis (BIRA); built-in self-repair (BISR); built-in self-test (BIST); embedded memories;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2005.848824

Filename

1458790